1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a plurality of data buses regularly arranged above a memory cell area.
2. Description of Related Art
A semiconductor memory device such as a DRAM (Dynamic Random Access Memory) has a memory cell area including many memory cells regularly arranged therein. A buffer area including a plurality of buffer circuits is placed near the memory cell area. The memory cells and the buffer circuits are connected through a plurality of data buses placed above the memory cell area. Because the many memory cells are regularly arranged in the memory cell area, the data buses are also regularly arranged (see Japanese Patent Application Laid-open No. 2006-253270).
The buffer circuits are connected to corresponding data buses, respectively, and thus the buffer circuits are also regularly arranged in general. For example, when an arrangement pitch of the buffer circuits is matched with an arrangement pitch of the data buses, the buffer circuits are arranged as extensions of the data bus, which achieves a simplest layout.
However, when the arrangement pitch of the buffer circuits is matched with the arrangement pitch of the data buses, layouts of other circuit blocks such as an internal voltage generating circuit are considerably limited. That is, because the memory cell area has an array area including many memory cells regularly arranged therein and a non-array area including a decoder and the like arranged therein, parts adjacent to the array area are all used as the buffer area when the arrangement pitch of the buffer circuits is matched with the arrangement pitch of the data buses. Accordingly, there is no choice but to arrange circuit blocks such as the internal voltage generating circuit adjacently to the non-array area, which causes a shortage of areas to be allocated to these circuit blocks. To compensate this situation, it is necessary to increase widths of the circuit blocks such as the internal voltage generating circuit and to deform a formation area thereof. In this case, a useless free space is produced due to a difference in width between the buffer area and the circuit blocks, resulting in increase in a chip area.
In another embodiment, such a semiconductor device is derived that includes: a plurality of buffer circuits each including first and second circuit nodes that are disposed substantially in line in a first direction; a plurality of first signal lines arranged at a first pitch in a second direction that is substantially perpendicular to the first direction, each of the first signal lines being elongated from the first circuit node of an associated one of the buffer circuits and running in the first direction on a side opposite to the second circuit node; a plurality of second signal lines arranged at the first pitch in the second direction, each of the second signal lines being elongated from the second circuit node of an associated one of the buffer circuits and running in the first direction on a side opposite to the first circuit node; a plurality of third signal lines arranged at a second pitch in the second direction, the second pitch being greater than the first pitch, each of the third signal lines running in the first direction; and a plurality of fourth signals each disposed between an associated one of the second signal lines and an associated one of the third signal lines to connect the associated one of the second signal lines and the associated one of the third signal lines to each other.